1. Field of the Invention
The present invention generally relates to a method of forming a semiconductor device. More specifically, the present invention relates to a method of forming a semiconductor device including a trench gate structure.
Priority is claimed on Japanese Patent Application No. 2007-297682, filed Nov. 16, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
Semiconductor devices such as DRAM (Dynamic Random Access Memory) may generally include transistors and capacitors. Shrinkage of a semiconductor device will shrink the dimensions of a transistor that is included in the semiconductor device. Shrinkage of the dimensions of the transistor may cause remarkable short channel effects. Shrinkage of memory cells would in general reduce the channel length of a transfer gate transistor that is included in every memory cell of the semiconductor device particularly in large capacity DRAMs. Reduction of the channel length of the transfer gate transistor would increase S-value of the transfer gate transistor. Increasing the S-value of the transfer gate transistor may deteriorate the retention and writing performance of the memory cell.
Trench gate transistors with three dimensional channel structures have been known for countermeasure to the short channel effects of the transistor and/or for improvement in refresh properties of the DRAM. The trench gate transistor has a channel which extends along the side walls of a trench groove that is formed in a semiconductor substrate, so as to ensure the adequate channel length thereof. The trench gate structure can suppress the short channel effects of the transistor and may improve the refresh properties. The trench gate structure will ensure longer channel length that may allow reducing channel dose, thereby allowing field relaxation at p-n junctions of source/drain regions. The field relaxation will improve the refresh properties.
Japanese Unexamined Patent Application, First Publication, No. 2006-108243 discloses a semiconductor manufacturing method for a trench transistor in which an ozone treatment process is carried out to form an oxide film before an anneal process is then carried out to cause reduction of the oxide film or remove the oxide film, prior to causing migration of silicon atoms.
Japanese Unexamined Patent Application, First Publication, No. 2004-140039 discloses a semiconductor manufacturing method for a trench transistor in which an anneal process is carried out in a reduction atmosphere, while trench upper corners are covered by masks of silicon nitride.
Japanese Unexamined Patent Application, First Publication, No. 2000-114362 discloses a semiconductor manufacturing method for a trench transistor in which the lower half of a trench is buried by a spin on glass and then the upper half of the trench is then buried by an oxide film.